In general, a TFT-LCD drive circuit drives a liquid crystal panel by (i) digitally processing a display signal, and (ii) converting, with a use of a DA converter, the digitally processed display signal into an analog voltage according to a display tone of the display signal. In recent years, a load of the liquid crystal panel has been increasingly becoming large for a drive circuit, with an increase in the size of the liquid crystal panel. On this account, in general, a low-output-impedance output circuit is formed as a voltage follower circuit by using an operational amplifier, and an output signal from the DA converter is input to this low-output-impedance output circuit. Thus, the output signal from the DA converter is converted into an output signal from the low-output-impedance output circuit, and this output signal from the output circuit is used for driving a liquid crystal panel.
FIG. 19 illustrates an exemplary configuration of a TFT-LCD module. In the TFT-LCD module, a liquid crystal panel 101 is driven by a plurality of gate driver circuits 103 and a plurality of source driver circuits 104, each of which is controlled by a control circuit 102.
FIG. 20 illustrates a configuration of each of the source driver circuits 104. Each source driver circuit 104 includes, sequentially from a side of the control circuit 102 towards a side of the liquid crystal panel 101: shift registers 104a; sampling latch circuits 104b; hold latch circuits 104c; level shifter circuits 104d; DA converters 104e; and output amplifiers 104f. 
Further, FIG. 21 illustrates an exemplary configuration of the TFT-LCD source driver circuit 104 for each output terminal. In the following explanation with reference to FIG. 21, it is assumed that display data is in 6 bits. For each bit of the 6-bit display data, one of the sampling latch circuits 104b, one of the hold latch circuits 104c, and one of the level shifter circuits 104d are provided.
Each bit of the display data is sampled in the sampling latch circuit 104b in response to an input of a start pulse signal (not shown) forwarded via the shift register 104a. Then, in the hold latch circuit 104c, each of the 6 bits is latched in response to a latch signal (horizontal synchronization signal) (not shown). After a signal level of the display data is converted in the level shifter circuit 104d, a voltage for tone display is selected in the DA converter 104e, in accordance with the display data (6 bits in this case). Then, the selected voltage for tone display is output to the liquid crystal panel 101, from the output amplifier 104f which is configured by a voltage follower circuit.
In FIG. 21, the shift register 104a, the sampling latch circuit 104b, and the hold latch circuit 104c are conventionally logical circuits. Further, the DA converter 104e and the output amplifier 104f are analog circuits. As described above, the output amplifier 104f is usually a voltage follower circuit which is configured by an operational amplifier. The level shifter circuit 104d is provided between the logical circuit and the analog circuit. This level shifter circuit 104d converts a voltage level of a logical signal into a voltage level for displaying images on the liquid crystal panel 101. An LSI of the TFT-LCD source driver circuits 104 (hereinafter referred to as a source driver LSI) includes therein a plurality of the circuits illustrated in FIG. 21, and an output voltage of each of the circuits drives each display data line of the liquid crystal panel 101.
Ideally, a voltage output from the voltage follower circuit (i.e. output amplifier 104f) which is configured by the operational amplifier is equal to a voltage input to the voltage follower circuit. However, in an actual LSI, due to a production variation, there is a random variation in the voltages respectively output from the operation amplifiers in the LSI. This random variation is called “offset variation”. If this offset variation occurs in the source driver LSI, drive voltages to be respectively applied to the display data lines of the liquid crystal panel 101 vary on a line-by-line basis. The display brightness of the liquid crystal panel 101 is controlled by the drive voltage applied to the display data line. Thus, the line-by-line variation in the drive voltages applied to the data lines causes a non-uniform display. Accordingly, in the source driver LSI, the variation in the output voltages respectively from the plurality of the liquid crystal driving voltage output terminals needs to be restrained to a level at which the display quality is not affected.
This offset variation of the operational amplifier in the source driver LSI is mainly attributed to a difference (mismatching) in finish properties of paired elements whose properties are supposed to be identical. In general, such an offset variation has been reduced as follows. Namely, the size of a circuit element constituting an operational amplifier is enlarged, and an extra caution is taken for arrangement of the circuit element in a layout designing process using a mask. Further, an offset adjustment circuit is added for adjusting an offset in an amplifier. For the offset adjustment circuit, various conventional methods are suggested.
FIG. 16 illustrates a first example of a conventional offset adjustment circuit (see Patent Document 1 (published Japanese translation of PCT international publication for patent application: Tokuhyo 2004-519969 (published on Jul. 2, 2004)). FIG. 16 illustrates: a common phase input terminal IN101; a negative-phase input terminal IN102; an output terminal OUT101; and a capacitor C101 for storing and retaining therein an offset adjustment voltage. Further, the offset adjustment circuit of FIG. 16 includes two switching elements S101 and a single switching element S102. Note that, in the present specification, including the description regarding this example, an input terminal of an operational amplifier is referred to as non-inverting input terminal and inverting input terminal, and is distinguished from: a common phase input terminal for inputting a signal to the non-inverting input terminal; and a negative-phase input terminal for inputting a signal to the inverting input terminal, unless otherwise notified.
The capacitor C101 is provided between (i) the inverting input terminal of the operational amplifier 111 and (ii) the negative-phase input terminal IN102. Further, one of the switching elements S101 is provided between the common phase input terminal IN101 and a point between the capacitor C101 and the negative-phase input terminal IN102. Another one of the switching elements S101 is provided between the output terminal of the operational amplifier 111 and the inverting input terminal of the operational amplifier 111. The switch S102 is provided between the negative-phase input terminal IN102 and the capacitor C101. Further, the offset voltage of the operational amplifier 111 is a voltage source Voff located between the non-inverting input terminal of the operational amplifier 111 and the common phase input terminal IN101.
This circuit adjusts an offset by alternating between (i) a storing state during which an offset adjustment voltage is stored, and (ii) a normal state during which the circuit serves as an ordinal operational amplifier. The switches S101 are closed, and the switch S102 is opened. Thus, the circuit enters the storing state. At this point, both ends of the capacitor C101 are charged by the electric potential of the offset voltage Voff. Then, the switches S101 are opened and the switch S102 is closed. Thus, the circuit enters the normal state. At this point, a difference between the electrical potentials at the both ends of the capacitor C101 equals to the Voff. Therefore, the offset voltage is cancelled.
FIGS. 17 and 18 illustrate second examples of conventional offset adjustment circuits. FIG. 17 illustrates an exemplary configuration of a CMOS operational amplifier circuit to which an offset adjustment circuit is added. FIG. 18 illustrates an application example where the circuit of FIG. 17 is applied to a voltage follower circuit.
The operational amplifier circuit of FIG. 17 includes: adjustment input terminals AUX1 and AUX2 for use in offset adjustment; a common phase input terminal IN111 (corresponding to a non-inverting input terminal); and a negative-phase input terminal IN112 (corresponding to an inverting input terminal). This operational amplifier circuit further includes: a first difference input pair including NMOS transistors T102 and T103; and a second difference input pair including NMOS transistors T105 and T106. The first difference input pair takes, as a bias current, a drain current of an NMOS transistor T101, and the second difference input pair takes, as a bias current, a drain current of an NMOS transistor T104. Further, the first and second difference input pairs share a common active load which is a current mirror circuit including PMOS transistors T107 and T108. The first difference input pair serves as an input section of the offset adjustment circuit. The gate terminal of the NMOS transistor T102 is connected to the common phase input terminal IN111, and the gate terminal of the NMOS transistor T103 is connected to the negative-phase input terminal IN112. The second difference input pair serves as an input section for an offset adjustment voltage. The gate terminal of the NMOS transistor T105 is connected to the adjustment input terminal AUX1, and the gate terminal of the NMOS transistor T106 is connected to the adjustment input terminal AUX2.
Further, the offset adjustment circuit includes an output transistor which is the PMOS transistor T110. This output transistor takes, as a bias current, a drain current of the NMOS transistor T109. The gate terminal of the PMOS transistor T110 is connected to (i) the drain terminal of the NMOS transistor T102 of the first difference input pair and (ii) the drain terminal of the NMOS transistor T105 of the second difference input pair. A voltage to be applied to the gate terminal of the PMOS transistor T110 is determined based on (i) a drain current flowing in the first difference input pair, and (ii) a drain current flowing in the second difference input pair. Based on this voltage, a current to be output from the drain terminal of the PMOS transistor T110 is determined, the drain terminal being connected to the output terminal OUT111 which serves as an output terminal of the offset adjustment circuit.
In the application example illustrated in FIG. 18, the offset adjustment circuit of FIG. 17 is used as an operational amplifier 121. Further, three switching elements S121, a single switching element S122, and capacitors C111 and C112 are provided around the operational amplifier 121. A non-inverting input terminal of the operational amplifier 121 corresponds to the common phase input terminal IN111 of FIG. 17, and an inverting input terminal of the operational amplifier 121 corresponds to the negative-phase input terminal IN112 of FIG. 17. The offset voltage of the operational amplifier 121 is a voltage source Voff provided between (i) a non-inverting input terminal of the operational amplifier 121 and (ii) an input terminal IN121 of the voltage follower circuit.
Here, the point-A is a node via which the input terminal IN121 and the voltage source Voff are connected with each other, and the point-B is the inverting input terminal of the operational amplifier 121. One of the switching elements 121 is provided between the point-A and the point-B. Further, the switching element 122 is provided between the point-B and the output terminal of the operational amplifier 121.
The capacitor C111 is provided between an adjustment input terminal AUX1 and a GND, and the capacitor C112 is provided between the adjustment input terminal AUX2 and the GND. Another one of the switching elements S121 is provided between the point-A and the adjustment input terminal AUX1, and further another one of the switching elements S121 is provided between an output terminal OUT121 of the voltage follower circuit and the adjustment input terminal AUX2.
Next, the following describes an operation of the voltage follower circuit illustrated in FIG. 18.
This circuit adjusts an offset by alternating between (i) a storing state during which an offset adjustment voltage is stored and (ii) a normal state during which the circuit serves as an ordinal operational amplifier. The switching elements S121 are closed and the switching element S122 is opened. Thus, the circuit enters the storing state. At this time, the point-A and the point-B are short-circuited, and have the same electric potential. An input voltage is applied to the adjustment input terminal AUX1, and is stored in the capacitor C111. Further, an output voltage of the operational amplifier 121 is fed back to the adjustment input terminal AUX2. The operational amplifier 121 is a circuit whose difference input terminal is the adjustment input terminals AUX1 and AUX2, and serves as a voltage follower. The output voltage of this operational amplifier 121 is stored in the capacitor C112. The voltage stored at this time in the capacitor C112 is a voltage for balancing the operational amplifier 121 while the voltages at the point-A and the point-B are the same.
Next, the switching elements S121 are opened, and the switching element S122 is closed. Thus, the operational amplifier enters the normal state. The point-B and the output terminal of the operational amplifier 121 (i.e. the output terminal OUT121) are short-circuited via the switching element S122. The capacitor C111 and C112 store and maintain such an electric potential that voltages at the point-A and the point-B are equal to each other. As a result, the same voltage as the voltage at the point-A is output to the output terminal OUT 121 which has been short-circuited to the point-B. Thus, an output from the voltage follower has no offset voltage.
Other than the above described techniques, various methods and/or configurations for offset adjustment are disclosed in: Patent Document 1, Patent Document 2 (Japanese Unexamined Patent Publication No. 274605/1992 (Tokukaihei 4-274605; published on Sep. 30, 1992), and Patent Document 3 (Japanese Unexamined Patent Publication No. 314490/1994 (Tokukaihei 6-314490; published on Nov. 8, 1994). All the methods and configurations disclosed in these documents adjust an offset by storing, in a capacitor, an offset adjustment voltage of an operational amplifier. Despite the variety in the circuit configurations, any of these methods are based on the following principle. Namely, while a common phase input terminal and a negative-phase input terminal are short-circuited, (i) a negative feedback process is carried out with respect to an offset adjusting terminal so that an output voltage of an operational amplifier is balanced at a medium electric potential between positive and negative power source voltages, and (ii) the voltage is stored in a capacitor. In these methods, an offset is adjusted by periodically alternating a state of an offset adjustment circuit, between (i) a storing state during which an offset adjustment voltage is stored and (ii) a normal state during which the offset adjustment circuit serves as an ordinal operational amplifier.
Conventionally, an offset variation among drive terminals in a source driver LSI has been reduced by: (i) increasing the size of a configuring element which influences a random variation, so that a matting is improved; and/or (ii) designing a circuit in consideration of a symmetrical property of a mask layout for an LSI. These methods, however, lead to an increase in the size of a chip and in production costs, when an offset adjustment circuit is formed into an LSI.
Another method for reducing the offset variation is to provide an offset adjustment circuit in a source driver LSI. A conventional offset adjustment circuit adjusts an offset by storing in a capacitor an offset adjustment voltage of an operational amplifier. Such an offset adjustment circuit includes a capacitor for offset adjustment, and a switching element. In an LSI having a typical CMOS configuration, the switching element is an MOS-FET. In the MOS-FET switch, a phenomenon so-called gate feed through occurs. This gate feed through is a phenomenon in which a charge is injected through a parasitic capacitance or the like, which capacitance is caused by a change in an electrical potential of a gate signal. Due to the charge injection, an amount of charge stored in an offset adjustment capacitor deviates from an expected amount. For the purpose of reducing such an influence, it has been suggested that a capacitor be enlarged, and that an offset adjustment voltage be sampled by using a differential circuit, as in the second example of the offset conventional adjustment circuit. However, in either case, an increase in a circuit scale is inevitable. This leads to an increase in a chip size and to an increase in production costs, when an offset adjustment circuit is formed into an LSI.
Further, a voltage to be stored in a capacitor is an analog voltage according to an offset voltage of an operational amplifier. This voltage to be stored in a capacitor varies with elapse of time due to a leak current or the like. It is therefore necessary to periodically refresh the voltage stored in the capacitor. On this account, in the configuration using a capacitor, an offset is adjusted by repetitively alternating the state of the offset adjustment circuit between (i) a storing state during which an offset adjustment voltage is stored and (ii) a normal state during which the offset adjustment circuit functions as an ordinal operational amplifier. During the offset adjustment voltage storing state, the offset adjustment circuit is not able to function as an ordinal amplifier. As such, period during which an output signal cannot be used periodically occurs.
A period for applying a display voltage to each pixel has been shortened in a recent enlarged liquid crystal panel whose number of display pixels has been increased. Therefore, it is necessary to apply a voltage at a high speed. For this reason, a liquid crystal drive circuit is preferably capable of carrying out a continuous voltage output. This makes it extremely difficult to adopt the conventional offset adjustment circuit. In order to solve this problem, it is suggested that two pairs of circuits be prepared, and that the two pairs of circuits alternately carry out an output drive and offset adjustment, thereby realizing the continuous driving. However, this method doubles a circuit scale. Therefore, an increase in costs is inevitable.